MAX1011CEG+【PDF 6/12 页】IC ADC 6BIT 90MSPS 24-QSOP

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MAX1011

Low-Power, 90Msps, 6-Bit ADC

_______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS

(VCC = +5V ±5%, VCCO = 3.3V ±300mV, TA = +25°C, unless otherwise noted.)

Note 1: Best-fit straight-line linearity method.

Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).

However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-

mode input range (Figures 4 and 5).

Note 3: PSRR is defined as the change in the mid-gain, full-scale range as a function of the variation in VCC supply voltage,

expressed in decibels.

Note 4: The current in the VCCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran-

sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig-

ital outputs to a minimum.

Note 5: Offset-correction compensation enabled, 0.22F at compensation inputs (Figures 2 and 3).

Note 6: tPD and tSKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a

data bit. tDCLK is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-

itive load on the outputs is 15pF.

GAIN = GND, open, VCC

GAIN = open (mid gain), fIN = 50MHz,

-1dB below full scale

GAIN = open (mid gain)

5.7

ENOBM

5.6

5.85

Effective Number of Bits

GAIN = open (mid gain)

GAIN = GND (low gain)

Guaranteed by design

CONDITIONS

MHz

Analog Input -0.5dB Bandwidth

Msps

fMAX

Maximum Sample Rate

GAIN = VCC (high gain)

LSB

OFF

Input Offset (Note 5)

-0.5

0.5

35.5

SINAD

Signal-to-Noise Plus Distortion

Ratio

Bits

5.85

ENOBL

5.8

ENOBH

(Note 6)

tSKEW

Data Valid Skew

3.0

tPD

Clock to Data Propagation

Delay

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

TNK+ to DCLK (Note 6)

4.5

tDCLK

Input to DCLK Delay

Figure 8

5.5

tAD

Aperture Delay

Figure 8

clock

cycle

Pipeline Delay

TIMING CHARACTERISTICS (Data outputs: RL = 1M, CL = 15pF)

DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), VIN = 20MHz sine, amplitude -1dB below

full scale, unless otherwise noted.)

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